1. Field of the Invention
This invention relates to a semiconductor data storage device including both non-volatile and volatile semiconductor storage elements.
2. Description of the Related Art
FIG. 7 is a circuit diagram showing a memory card which constitutes an example of a conventional semiconductor storage device of this type. This card is detachably connected to an external device such as a reader/writer (not shown) and supplied with electrical power and various control signals from the external device, and writing and reading of data is performed in accordance with these signals. When the card is not connected to the external device, data is retained in the card by a back-up internal power source for memory backup that is provided in the card. In the drawing, numeral 1 indicates a power control circuit; numeral 2 indicates an address decoder; numeral 3 indicates an address buffer; numerals 4a and 4b indicate non-volatile semiconductor storage elements; numerals 5a and 5b indicate volatile semiconductor storage elements; numerals 6a, 6b, 7a, 7b, 8 and 9 indicate tri-state buffers; numeral 10 indicates an external power line; numeral 11 indicates a grounding line; numerals 12a and 12b indicate high-order address signal lines (AO, A1); numeral 13 indicates a card enable signal line (CE); numeral 14 indicates an address bus (ADD); numeral 15 indicates an output enable signal line (OE); numeral 16 indicates a write enable signal line (WE); numeral 17 indicates an internal signal line; numeral 18 indicates a reset signal line (RST); numeral 19 indicates an internal address bus; numeral 20 indicates a data bus (DATA); numerals 21a, 21b, 22a and 22b indicate memory chip enable signal lines (MCE); numeral 23 indicates a memory output enable signal line (MOE); numeral 24 indicates a memory write enable signal line (MWE); numerals 25a, 25b, 26a, 26b, 27 and 28 indicate pull-up resistors; and numeral 29 indicates an internal power source. In the following description, signal lines and signals transmitted therethrough are referred to by the same reference numerals. The circuit shown is a negative logic circuit.
The power control circuit 1 detects the voltage of the external power line 10 to connect either the external power line 10 or the internal power source 29 to the internal power line 17 in accordance with the voltage detected. That is, when the card can be supplied with power from the external device, the external power line 10 is connected to the internal power line 17 and, when the card cannot be supplied with power from the external power source, the internal power source 29, generally consisting of a battery contained in the card, is connected to the internal power line 17. Further, the power control circuit 1 generates a reset signal (RST), which is at "L" level when the card can be supplied with power from the external power source, and at "H" level when the card is being supplied with power from the internal power source 29. Signals on lines 12a, 12b, 13, 14, 15, and 16 for memory control signals supplied from an external device for reading and writing of data with respect to the card. Input and output of data to and from the card is effected through the data bus 20. The card enable signal on line 13 (CE) makes the card ready for operation. The high-order address signal lines 12a and 12b (AO and A1) set addresses in the storage area of the card. In accordance with the high-order address signals on lines 12a and 12b, a predetermined storage element is made ready for operation and, by an address signal on line 14 (ADD), an address in the storage element is designated. The output enable signal on line 15 (OE) and the write enable signal on line 16 (WE) permit writing and reading of data, respectively. The address decoder 2 is made ready for operation by the card enable signal on line 13 (CE) at "L" level, and sets one of the memory chip enable signals on lines 21a, 21b, 22a and 22b (MCE) to "L" level in accordance with the high-order address signals on lines 12a and 12b (AO and A1). The memory chip enable signals on lines 21a, 21b, 22a and 22b are transmitted through the tri-state buffers 6a, 6b, 7a and 7b to the storage elements 4a, 4b, 5a and 5b, respectively, and the storage element which receives the "L" level memory chip enable signal is activated.
The address bus buffer 3 supplies the input address signal on line 14 (ADD) to each storage element as an internal address signal on line 19. The internal address signal on line 19 sets a data address in the storage element. The output enable signal on line 15 (OE) and the write enable signal on line 16 (WE) are supplied through the tri-state buffers 8 and 9, respectively, to the storage elements as a memory output enable signal on line 23 (MOE) and a memory write enable signal on line 24 (MWE). The reset signal on line 18 (RST) is input to the control terminal of each of the tri-state buffers 6a, 6b, 7a, 7b, 8 and 9. When the reset signal on line 18 (RST) is at "L" level, the input signal is output as it is, and, when the reset signal is at "H" level, the output line is brought to a high-impedance state ("Hz"). To determine the level of the signal lines in the high-impedance state, the pull-up resistors 25a, 25b, 26a, 26b, 27 and 28, which are connected to the external power line 10 or the internal power line 17, are respectively connected to the memory chip enable signal lines 21a, 21b, 22a and 22b, the memory output enable signal line 23 and the memory write enable signal line 24. The external power line 10 having no backup is indicated by a circle whereas the internal power line 17 with backup is indicated by a square. The non-volatile semiconductor storage elements 4a and 4b and the address bus buffer 3 are connected to the external power line 10, whereas the volatile semiconductor storage elements 5a and 5b and the address decoder 2 are connected to the internal power line 17 with backup.
Next, the operation of this IC memory card will be described. When the IC memory card is connected to the external device (not shown) and voltage is supplied to the external power line 10 from the external power source, the voltage control circuit 1 switches the power source from the internal power source 29 to the external power line 10. At this time, the reset signal on line 18 (RST) changes from "H" to "L" level, whereby each of the tri-state buffers 6a, 6b, 7a, 7b, 8 and 9 is activated. In this condition, the semiconductor storage elements 4a, 4b, 5a and 5b can be selectively accessed for writing or reading of data through control of the card enable signal on line 13, the address signal on line 14, the high-order address signal on lines on line 12a and 12b, output enable signal on line 15 and the write enable signal on line 16. The address decoder 2 sets a predetermined one of its four output terminals (YO), (Y1), (Y2) and (Y3) to "L" level in accordance with the 2-bit high-order address signals on line 12a and 12b. The storage element receiving the "L" level memory chip enable signal (MCE) is activated. Input and output of data to and from each storage element is effected through the data bus 20, and data is written to an address designated by the internal address signal on line 19 or read from the address.
When the IC memory card is detached from the external device and the power supply from the external power source is stopped, the power control circuit 1 switches the power source to the internal power source 29. At this time, the reset signal on line 18 (RST) changes from "L" to "H" level, whereby the output lines of the tri-state buffers 6a, 6b, 7a, 7b, 8 and 9 are all brought to a high-impedance state ("Hz"). The memory chip enable signal lines 22a and 22b and the memory write enable signal line 24 are connected to the internal power line 17 having backup through the pull-up resistors 26a, 26b and 28, so that they are maintained at "H" level, whereby the volatile semiconductor storage elements 5a and 5b are kept in a condition in which it is impossible to perform writing or reading, data being retained by the power from the internal power source 29 connected to the internal power line 17. The non-volatile semiconductor storage devices 4a and 4b need no data backup. To further reduce the power consumption when the card is not being used, the memory chip enable signal lines 21a and 21b are connected to the external power line 10 having no power backup through the pull-up resistors 25a and 25b. The memory output enable signal line 23 is also connected to the external power line 10 having no backup through the pull-up resistor 27.
In the conventional semiconductor storage device, constructed as described above, the level of each control signal line when connecting and disconnecting the external power source is controlled by a pull-up resistor, so that the level of each signal line does not change rapidly. Therefore, when the external power source is suddenly switched off during, for example, data writing, it takes a long time for the memory chip enable signal lines and the memory write enable signal line of the volatile semiconductor storage elements to reach "H" level, resulting in erroneous writing, etc.
This will be explained with reference to FIG. 8. Assuming that the external power source is switched off at time T1 during writing of data, the power source voltage Vcc starts to fall. When the power control circuit 1 detects at time T2 that the power source voltage Vcc has become lower than a predetermined value, the reset signal changes from "L" to "H" level, whereby the output side of each tri-state buffer is brought to a high-impedance state ("Hz"), and the memory chip enable signal lines 21a and 21b (MCE) and the memory output enable signal line 23 (MOE), connected to the external power line 10 without backup, are gradually brought to "L" level. In contrast, the memory chip enable signal lines 22a and 22b (MCE) and the memory write enable signal line 24 (MWE), connected to the internal power line 17 having backup, are gradually brought to "H" level. The memory chip enable signal lines 22a and 22b (MCE) and the memory write enable signal line 24 (MWE) for the volatile semiconductor storage elements 5a and 5b are at "L" level during writing. When the external power line is switched off, they rise from "L" to "H" level. This rise in level, however, does not take place quickly, so that erroneous writing may occur before "H" level is attained.
Immediately after the connection of the external power source to the IC memory card, the memory chip enable signal lines 21a and 21b (MCE) and the memory output enable signal line 23 (MOE) for the non-volatile semiconductor storage elements change from "L" to "H" level, so that the two non-volatile semiconductor storage elements 4a and 4b may be simultaneously ready for operation, resulting in contention of data in the data bus 20, etc.